FIG. 1 shows a typical (prior art) analog-to-digital converter (ADC) system, which may operate from a single two-terminal power supply source providing a high supply voltage bias (say, 5V) and a low supply voltage bias (0V, ground). An amplifier circuit [100] is an active circuit providing an analog voltage signal Vin(t). Amplifier circuit [100] receives the high supply voltage bias (5V) via a first power supply terminal [101] and the low supply voltage bias (0V) via a second power supply terminal [102]. The analog voltage signal Vin(t) is provided as an input voltage signal to an ADC [103] that samples the analog voltage signal to acquire a sampled analog voltage Vin(k). ADC [103] provides a numerical (digital) representation D1(k) corresponding to (representing) the sampled analog voltage Vin(k). ADC [103] may use a successive-approximation algorithm to derive D1(k), but many other types of analog-to-digital conversion methods/circuits are known to those skilled in the art. ADC [103] receives a first reference voltage potential, Vref1, and a second reference voltage potential, Vref2, via a first reference voltage terminal [104] and a second reference voltage terminal [105]. The first reference voltage potential, Vref1, may be substantially the same as the low supply voltage bias (0V), and the second reference voltage potential, Vref2, may be provided by a conventional bandgap reference voltage generator circuit (not shown) connected to (powered by) the two-terminal power source. In a typical application, Vref2 may be slightly lower than the high supply voltage bias, for example Vref2=4.096V. ADC [103] is also connected to (powered by) the two-terminal power source via power supply terminals [107] and [106].
Numerical representation D1(k) may represent the sampled analog voltage Vin(k) with a resolution of N bits, where N is an integer number, for example N=4, 8, 16, or 18. D1(k) may be encoded in a straight-binary format, having two-to-the-power-of-N (2^N) distinct numerical values: 0, 1, 2, . . . , (2^N)−2, (2^N)−1. A normalized numerical representation may be derived by dividing the straight-binary representation by 2^N, whereby the possible numerical values are spaced uniformly with a numerical separation of 1/(2^N) in a numerical full-scale range having a lower limit, 0, and an upper limit, 1−1/(2^N). FIG. 2 shows the straight binary codes of D1(k) produced by an N=4 bit ADC [103] for a range of values of the sampled analog signal Vin(k).
A reference voltage range is delimited by a lower limit (Vref1=0V) and an upper limit (Vref2=4.096V). N=4 bit ADC [103] effectively divides the reference voltage range in 2^N=16 code-specific voltage ranges, each corresponding to a unique code and numerical value of D1(k), and each having a width equal to a least significant bit size. Sampled analog voltages Vin(k) greater than the upper limit of the reference voltage range, Vref2=4.096V, cause ADC [103] to saturate at a maximum digital code D1(k)=1111. Similarly, sampled analog voltages Vin(k) smaller than the lower limit of the reference voltage range, Vref1=0V, cause ADC [103] to saturate at a minimum digital code D1(k)=0000. These limits may be called saturation limits, which delimit a full-scale range of ADC [103].
A loss of information may occur if analog voltage signal Vin(t) exceeds the full-scale range of ADC [103]. Similarly, variations in Vin(k) that are smaller than the least significant bit size may not register (cause variations) in D1(k), which may also result in a loss of information. Accordingly, to reduce any loss of information, it may be desirable to maximize a full-scale range of Vin(t) without causing ADC [103] to saturate. Specifically, to optimize a dynamic range (a measure of performance) for the system of FIG. 1, it may be desirable to select a full-scale range for Vin(t) such that it is substantially the same as the full-scale range of ADC [103].
If active circuit [100] providing Vin(t), reference voltage generator (not shown) providing Vref2, and ADC [103] are all supplied power from a single two-terminal power source (e.g., a single battery), terminals [102], [104], and [106] may all be connected to a low supply voltage bias (0V, ground) provided by the single two-terminal power source. An active circuit, such as amplifier circuit [100], may not be able to drive/provide an analog voltage signal Vin(t) close to its power supply bias voltages without a significant loss of fidelity (information), implying that a full-scale range of Vin(t) may have to be smaller than the reference voltage range, thus limiting/reducing the dynamic range. This type of limitation may be overcome by providing a second power source providing a third supply voltage bias, say −5V, connected to power supply terminal [102] to drive amplifier [100], but that option is associated with additional cost, physical volume, power dissipation, and other disadvantages.
It is an object of this invention to provide an analog-to-digital converter (ADC) that facilitates optimizing a dynamic range for an ADC system powered by a single two-terminal power source.
It is another object of the invention to provide an ADC having a full-scale range confined within the limits of a single power supply voltage range, such that an active circuit (powered by the single power supply) can provide with good fidelity a voltage signal utilizing the entire full-scale range.
It is another object of the invention to improve the utility (e.g., provide programmable saturation/full-scale limits) of ADCs incorporated in systems powered by one or more power sources.
Additional objects and advantages of the present invention will be apparent from studying the appended figures, description, and claims.